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| IS61LV51216 512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES * High-speed access time: -- 8, 10, and 12 ns * CMOS low power operation * Low stand-by power: -- Less than 5 mA (typ.) CMOS stand-by * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available ISSI MARCH 2003 (R) DESCRIPTION The ISSI IS61LV51216 is a high-speed, 8M-bit static RAM organized as 525,288 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV51216 is packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 1 IS61LV51216 TRUTH TABLE WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISSI VDD Current ISB1, ISB2 ICC ICC (R) Mode Not Selected Output Disabled Read Write ICC PIN CONFIGURATIONS 44-Pin TSOP (Type II) PIN DESCRIPTIONS A0-A18 I/O0-I/O15 A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A14 A13 A12 A11 A10 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground CE OE WE LB UB NC VDD GND 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 IS61LV51216 PIN CONFIGURATIONS 48-Pin mini BGA (9mmx11mm) PIN DESCRIPTIONS A0-A18 1 2 3 4 5 6 ISSI Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground (R) 1 2 3 4 5 6 7 I/O0-I/O15 CE OE WE A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 A18 OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 GND A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 N/C I/O0 I/O2 LB UB NC VDD GND VDD GND I/O6 I/O7 NC ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter VTERM VDD TSTG PT Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value -0.5 to VDD+0.5 -0.3 to +4.0 -65 to +150 1.0 Unit V V C W 8 9 10 11 12 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 3 IS61LV51216 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V +10%, -5% 3.3V +10%, -5% ISSI (R) DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VDD GND VOUT VDD Outputs Disabled Com. Ind. Com. Ind. Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.3 -1 -5 -1 -5 Max. -- 0.4 VDD + 0.3 0.8 1 5 1 5 Unit V V V V A A Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB1 VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. VDD = Max., VIN = VIH or VIL CE VIH, f = 0 Com. Ind. -8 Min. Max. -- -- -- -- -- -- 110 120 30 35 20 25 -10 Min. Max. -- -- -- -- -- -- 100 110 30 35 20 25 -12 Min. Max. -- -- -- -- -- -- 90 100 30 35 20 25 Unit mA mA ISB2 VDD = Max., Com. CE VDD - 0.2V, Ind. VIN VDD - 0.2V, or VIN 0.2V, f = 0 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 IS61LV51216 CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI (R) 1 2 3 Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 4 5 6 7 319 50 1.5V 30 pF Including jig and scope AC TEST LOADS ZO = 50 OUTPUT 3.3V 8 5 pF Including jig and scope 353 OUTPUT 9 10 11 12 Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 5 IS61LV51216 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time -8 Min. Max. 8 -- 3 -- -- -- 0 0 3 -- 0 0 0 -- -- 8 -- 8 3.5 3 -- 3 -- 3.5 3 -- -- 8 -10 Min. Max. 10 -- 3 -- -- -- 0 0 3 -- 0 0 0 -- -- 10 -- 10 4 4 -- 4 -- 4 3 -- -- 10 -12 Min. Max. 12 -- 3 -- -- 0 0 0 3 -- 0 0 0 -- -- 12 -- 12 5 5 -- 6 -- 5 4 -- -- 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ISSI (R) tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 IS61LV51216 READ CYCLE NO. 2(1,3) ISSI tRC (R) 1 tOHA ADDRESS tAA OE 2 3 4 tDOE CE tHZOE tLZOE tACE tLZCE tHZCE LB, UB DOUT HIGH-Z tLZB tBA tRC DATA VALID tHZB 5 ICC 50% VDD Supply Current tPU 50% tPD ISB UB_CEDR2.eps 6 7 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 8 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 7 IS61LV51216 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End (2) ISSI -8 Min. Max. 8 6.5 6.5 0 0 6.5 6.5 8.0 5 0 -- 2 -- -- -- -- -- -- -- -- -- -- 3.5 -- -10 Min. Max. 10 8 8 0 0 8 8 10 6 0 -- 2 -- -- -- -- -- -- -- -- -- -- 5 -- -12 Min. Max. 12 8 8 0 0 8 8 12 6 0 -- 2 -- -- -- -- -- -- -- -- -- -- 6 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns (R) tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE tLZWE(2) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 IS61LV51216 AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) ISSI (R) 1 2 t HA t WC ADDRESS VALID ADDRESS t SA CE t SCE WE t AW t PWE1 t PWE2 t PBW 3 4 t LZWE HIGH-Z UB, LB t HZWE DOUT DATA UNDEFINED 5 t HD DATAIN VALID UB_CEWR1.eps t SD DIN 6 7 8 9 10 11 12 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 9 IS61LV51216 AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS ISSI (R) t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS LOW t HA LOW t AW t PWE2 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR3.eps 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 IS61LV51216 AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) t WC ADDRESS ADDRESS 1 ISSI (1,3) (R) 1 t WC ADDRESS 2 OE 2 t SA LOW CE WE t HA t SA t PBW t PBW WORD 2 t HA 3 4 5 UB_CEWR4.eps UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 11 IS61LV51216 ORDERING INFORMATION: Commercial Range: 0C to +70C Speed (ns) 8 10 12 Order Part No. IS61LV51216-8T IS61LV51216-8M IS61LV51216-10T IS61LV51216-10M IS61LV51216-12T Package TSOP (Type II) Mini BGA (9mm x 11mm) TSOP (Type II) Mini BGA (9mm x 11mm) TSOP (Type II) ISSI (R) Industrial Range: -40C to +85C Speed (ns) 8 10 12 Order Part No. IS61LV51216-8TI IS61LV51216-8MI IS61LV51216-10TI IS61LV51216-10MI IS61LV51216-12TI Package TSOP (Type II) Mini BGA (9mm x 11mm) TSOP (Type II) Mini BGA (9mm x 11mm) TSOP (Type II) 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. A 03/19/03 |
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